Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

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Information Technology Journal, 8, The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

The proposed reversible Baugh-Wooley multiplier design requires 16 constant inputs, but the design in [5] [7] – [9] requires 52, 40, 44 and 42 respectively. Hence this is also called as Swap gate.

One of the major factors in the design of a reversible logic circuit is the number of constant inputs. The quantum circuits can be constructed only with reversible logic gates.

Tab stop Adder electronics Field-programmable gate array Multiplication. This design is useful in the multiplier design with reduced number bzugh gates and constant inputs. The work [7] also follows the same strategy as the previous two works, multiplication in two steps.

This constraint forces the number of inputs to be equal to the number of outputs. The number of inputs and outputs are three in count; if the first two bits A and B are set, mlutiplier third bit will be inverted, otherwise all bits will keep on the same value.


World Applied Sciences Journal, 10, It is comprehended that the number of gates, the constant inputs and garbage outputs values are fewer in number in the proposed design compared to the existing approaches.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

The number of two-Qubit gates is This scenario motivates the study of reversible computing field. Optical News, 11, It has been done in two steps as follows: The input B is the multiplicand bit. World Applied Sciences Journal, 3, The number of gates, constant inputs and garbage outputs. The PFAG gate is used in the multi operand addition. These proposed multiplier cells are having one constant input. A detailed representation and explanation is done in this section.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

The final product could be generated by subtracting the mulhiplier two positive terms from the first two terms. The reversible multiplier designs available in the literature are for mkltiplier array multipliers. The input D is the sum input from the previous cells.

As a first step pad each of the last two terms in the product P with zeros to obtain a 2n-bit number to aid adding it with the other terms. The input A is the multiplier bit. The proposed reversible Baugh- Wooley multiplier design produces 48 garbage outputs, but the design in [5] [7] – [9] produces 52, 52, 40 and 49 garbage outputs respectively. The additional input that is included to the irreversible function to convert mmultiplier reversible is called constant input [4].


Measuring the reversible logic design in terms of number of gates is one of the major factors.

As the nano devices are developed, the density of digital chips is being increased naturally seeking the solution for the power consumption and the heat dissipation developed by this power consumption. To generate the partial products, 16 Peres gates have been used, for 16 one-bit multiplication arrays.

In [5]the design requires a total of 40 reversible gates, [9] requires 42, total number of multippier required is 44 in [7] and in [8] the number of gates required is 32 gates.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog – Semantic Scholar

However this work is compared and evaluated with the other array multiplier designs available in the literature. Since in reversible circuits the fan-out greater that one is not permitted, this gate is useful for duplicating the inputs.

In the block diagram shown in Figure 5three types of cells are used.